Sda Is High and Scl Low After First Read

Using the I2C Bus

Using the I2C Bus

Judging from my emails, it is quite clear that the I2C bus can exist very confusing for the newcomer. I have lots of examples on using the I2C coach on the website, but many of these are using high level controllers and exercise non show the detail of what is actually happening on the bus. This brusque article therefore tries to de-mystify the I2C bus, I promise it doesn't have the opposite upshot!

The physical I2C bus
This is just two wires, called SCL and SDA. SCL is the clock line. It is used to synchronize all information transfers over the I2C bus. SDA is the data line. The SCL & SDA lines are connected to all devices on the I2C autobus. There needs to be a tertiary wire which is just the ground or 0 volts. In that location may also be a 5volt wire is power is being distributed to the devices. Both SCL and SDA lines are "open bleed" drivers. What this means is that the scrap can drive its output depression, simply it cannot drive it high. For the line to be able to go high you must provide pull-up resistors to the 5v supply. There should be a resistor from the SCL line to the 5v line and another from the SDA line to the 5v line. You lot only need one set of pull-upward resistors for the whole I2C motorbus, not for each device, as illustrated below:

The value of the resistors is not disquisitional. I have seen anything from 1k8 (1800 ohms) to 47k (47000 ohms) used. 1k8, 4k7 and 10k are common values, merely anything in this range should work OK. I recommend 1k8 as this gives you the all-time performance. If the resistors are missing, the SCL and SDA lines will e'er exist low - nearly 0 volts - and the I2C bus will not work.

Masters and Slaves
The devices on the I2C coach are either masters or slaves. The chief is always the device that drives the SCL clock line. The slaves are the devices that respond to the master. A slave cannot initiate a transfer over the I2C passenger vehicle, only a chief can do that. There tin can exist, and usually are, multiple slaves on the I2C jitney, however at that place is normally simply one main. It is possible to accept multiple masters, but information technology is unusual and not covered here. On your robot, the primary will be your controller and the slaves volition be our modules such equally the SRF08 or CMPS03. Slaves will never initiate a transfer. Both master and slave can transfer information over the I2C bus, merely that transfer is always controlled by the master.

The I2C Physical Protocol
When the chief (your controller) wishes to talk to a slave (our CMPS03 for example) information technology begins by issuing a start sequence on the I2C bus. A beginning sequence is one of two special sequences defined for the I2C bus, the other beingness the cease sequence. The start sequence and stop sequence are special in that these are the only places where the SDA (data line) is allowed to change while the SCL (clock line) is loftier. When data is existence transferred, SDA must remain stable and not change whilst SCL is high. The starting time and stop sequences mark the outset and cease of a transaction with the slave device.

Information is transferred in sequences of viii $.25. The bits are placed on the SDA line starting with the MSB (Most Significant Bit). The SCL line is then pulsed high, and so low. Remember that the flake cannot really drive the line high, it simply "lets go" of it and the resistor actually pulls information technology loftier. For every 8 bits transferred, the device receiving the information sends dorsum an acknowledge flake, and then there are really 9 SCL clock pulses to transfer each viii bit byte of data. If the receiving device sends back a depression ACK bit, and then it has received the information and is ready to accept another byte. If it sends back a loftier then it is indicating information technology cannot accept whatsoever further data and the master should end the transfer by sending a stop sequence.

How fast?
The standard clock (SCL) speed for I2C up to 100KHz. Philips do define faster speeds: Fast fashion, which is upwardly to 400KHz and High Speed mode which is upwardly to 3.4MHz. All of our modules are designed to piece of work at up to 100KHz. Nosotros accept tested our modules upward to 1MHz merely this needs a pocket-sized filibuster of a few the states between each byte transferred. In practical robots, we take never had any need to use high SCL speeds. Go along SCL at or below 100KHz and then forget about it.

I2C Device Addressing
All I2C addresses are either vii bits or x bits. The apply of 10 bit addresses is rare and is not covered here. All of our modules and the common chips you will use volition have 7 bit addresses. This means that you can have up to 128 devices on the I2C coach, since a 7bit number tin can be from 0 to 127. When sending out the seven chip address, nosotros still always transport 8 $.25. The extra scrap is used to inform the slave if the master is  writing to it or reading from it. If the fleck is nothing the master is writing to the slave. If the bit is ane the master is reading from the slave. The 7 bit accost is placed in the upper 7 $.25 of the byte and the Read/Write (R/W) chip is in the LSB (Least Pregnant Fleck).

The placement of the 7 bit address in the upper 7 bits of the byte is a source of confusion for the newcomer. It means that to write to address 21, you must actually send out 42 which is 21 moved over by 1 bit. It is probably easier to recall of the I2C bus addresses as eight chip addresses, with even addresses as write only, and the odd addresses as the read accost for the same device. To take our CMPS03 for example, this is at address 0xC0 ($C0). You would uses 0xC0 to write to the CMPS03 and 0xC1 to read from it. So the read/write bit merely makes it an odd/even address.

The I2C Software Protocol
The first matter that will happen is that the master will ship out a start sequence. This volition alert all the slave devices on the motorcoach that a transaction is starting and they should listen in incase information technology is for them. Adjacent the master volition transport out the device address. The slave that matches this address will keep with the transaction, any others will ignore the balance of this transaction and look for the next. Having addressed the slave device the master must at present send out the internal location or annals number within the slave that information technology wishes to write to or read from. This number is obviously dependant on what the slave actually is and how many internal registers it has. Some very simple devices do non have any, but most do, including all of our modules. Our CMPS03 has 16 locations numbered 0-fifteen. The SRF08 has 36. Having sent the I2C address and the internal register address  the chief can now send the information byte (or bytes, it doesn't accept to exist simply one). The master can keep to send information bytes to the slave and these volition normally be placed in the following registers because the slave will automatically increment the internal annals address after each byte. When the master has finished writing all data to the slave, it sends a cease sequence which completes the transaction. So to write to a slave device:
ane. Send a start sequence
2. Send the I2C address of the slave with the R/West bit low (even address)
3. Send the internal register number y'all want to write to
4. Send the data byte
five. [Optionally, ship whatever further data bytes]
6. Send the end sequence.

As an example, you take an SRF08 at the manufacturing plant default address of 0xE0. To outset the SRF08 ranging you would write 0x51 to the command register at 0x00 like this:
1. Ship a start sequence
2. Transport 0xE0 ( I2C address of the SRF08 with the R/Due west bit depression (even address)
3. Send 0x00 (Internal address of the command annals)
4. Send 0x51 (The command to start the SRF08 ranging)
5. Send the stop sequence.

Reading from the Slave
This is a little more complicated - only not too much more. Before reading information from the slave device, you lot must tell it which of its internal addresses yous want to read. And then a read of the slave actually starts off past writing to it. This is the same as when you lot want to write to it: You send the offset sequence, the I2C address of the slave with the R/Westward bit low (even address) and the internal register number you desire to write to. Now yous ship another commencement sequence (sometimes called a restart) and the I2C address once again - this fourth dimension with the read bit fix. Y'all and so read as many data bytes as you wish and terminate the transaction with a stop sequence. And then to read the compass begetting as a byte from the CMPS03 module:
ane. Send a start sequence
ii. Transport 0xC0 ( I2C accost of the CMPS03 with the R/W bit low (even accost)
iii. Send 0x01 (Internal address of the bearing register)
4. Send a kickoff sequence again (repeated start)
5. Send 0xC1 ( I2C address of the CMPS03 with the R/W bit loftier (odd address)
6. Read data byte from CMPS03
seven. Ship the end sequence.

The chip sequence volition expect like this:

Wait a moment
That's almost it for simple I2C communications, just there is ane more complication. When the master is reading from the slave, its the slave that places the data on the SDA line, but its the primary that controls the clock. What if the slave is not ready to send the data! With devices such as EEPROMs this is not a problem, but when the slave device is really a microprocessor with other things to exercise, it tin exist a problem. The microprocessor on the slave device will need to go to an interrupt routine, save its working registers, find out what accost the master wants to read from, get the data and place information technology in its manual annals. This tin can have many uS to happen, meanwhile the master is blissfully sending out clock pulses on the SCL line that the slave cannot respond to. The I2C protocol provides a solution to this: the slave is allowed to concord the SCL line depression! This is called clock stretching. When the slave gets the read command from the master it holds the clock line depression. The microprocessor then gets the requested information, places information technology in the manual register and releases the clock line allowing the pull-up resistor to finally pull it high. From the masters point of view, it will issue the first clock pulse of the read past making SCL high and so cheque to encounter if information technology really has gone high. If its still low and then its the slave that holding information technology depression and the master should expect until information technology goes high earlier continuing. Luckily the hardware I2C ports on most microprocessors volition handle this automatically.

Sometimes even so, the master I2C is just a collection of subroutines and there are a few implementations out at that place that completely ignore clock stretching. They work with things like EEPROM's but not with microprocessor slaves that use clock stretching. The consequence is that erroneous data is read from the slave. Beware!

Example Master Code
This case shows how to implement a software I2C master, including clock stretching. It is written in C for the Motion picture processor, but should exist applicable to almost processors with minor changes to the I/O pin definitions. It is suitable for controlling all of our I2C based robot modules. Since the SCL and SDA lines are open up bleed type, we utilize the tristate command register to command the output, keeping the output register low. The port pins even so need to be read though, then they're defined as SCL_IN and SDA_IN. This definition and the initialization is probably all you'll demand to change for a unlike processor.

#define SCL     TRISB4 // I2C double-decker
#define SDA     TRISB1 //
#ascertain SCL_IN  RB4    //
#define SDA_IN  RB1    //

To initialize the ports set the output resisters to 0 and the tristate registers to one which disables the outputs and allows them to be pulled high by the resistors.
SDA = SCL = 1;
SCL_IN = SDA_IN = 0;We use a modest filibuster routine between SDA and SCL changes to requite a articulate sequence on the I2C motorbus. This is cipher more than a subroutine telephone call and return.
void i2c_dly(void)
{
}

The following 4 functions provide the primitive start, stop, read and write sequences. All I2C transactions can be built upwardly from these.
void i2c_start(void)
{
  SDA = 1;             // i2c outset bit sequence
  i2c_dly();
  SCL = 1;
  i2c_dly();
  SDA = 0;
  i2c_dly();
  SCL = 0;
  i2c_dly();
}

void i2c_stop(void)
{
  SDA = 0;             // i2c stop bit sequence
  i2c_dly();
  SCL = one;
  i2c_dly();
  SDA = 1;
  i2c_dly();
}

unsigned char i2c_rx(char ack)
{
char ten, d=0;
  SDA = one;
  for(x=0; 10<eight; ten++) {
    d <<= 1;
    do {
      SCL = 1;
    }
    while(SCL_IN==0);    // await for any SCL clock stretching
    i2c_dly();
    if(SDA_IN) d |= 1;
    SCL = 0;
  }
  if(ack) SDA = 0;
  else SDA = 1;
  SCL = i;
  i2c_dly();             // transport (N)ACK bit
  SCL = 0;
  SDA = 1;
  return d;
}

bit i2c_tx(unsigned char d)
{
char x;
static flake b;
  for(x=viii; x; 10--) {
    if(d&0x80) SDA = ane;
    else SDA = 0;
    SCL = 1;
    d <<= 1;
    SCL = 0;
  }
  SDA = 1;
  SCL = 1;
  i2c_dly();
  b = SDA_IN;          // possible ACK flake
  SCL = 0;
  return b;
}

The iv primitive functions above can easily exist put together to class complete I2C transactions. Here'south and instance to first an SRF08 ranging in cm:

i2c_start();              // transport starting time sequence
i2c_tx(0xE0);             // SRF08 I2C accost with R/W bit clear
i2c_tx(0x00);             // SRF08 command register address
i2c_tx(0x51);             // command to commencement ranging in cm
i2c_stop();               // send stop sequence

Now after waiting 65mS for the ranging to complete (I've left that to you) the following instance shows how to read the low-cal sensor value from register 1 and the range result from registers ii & 3.

i2c_start();              // transport first sequence
i2c_tx(0xE0);             // SRF08 I2C address with R/W flake articulate
i2c_tx(0x01);             // SRF08 light sensor register address
i2c_start();              // send a restart sequence
i2c_tx(0xE1);             // SRF08 I2C address with R/W bit ready
lightsensor = i2c_rx(one);  // get lite sensor and send acknowledge. Internal annals address will increment automatically.
rangehigh = i2c_rx(i);    // become the high byte of the range and send acknowledge.
rangelow = i2c_rx(0);     // go low byte of the range - note we don't acknowledge the last byte.
i2c_stop();               // transport stop sequence

Easy isn't it?

The definitive specs on the I2C bus can be establish on the Philips website. It currently here but if its moved you'll find information technology easily be googleing on "i2c bus specification".

Sda Is High and Scl Low After First Read

Source: https://www.robot-electronics.co.uk/i2c-tutorial

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